Free Access
Issue
RAIRO-Theor. Inf. Appl.
Volume 29, Number 6, 1995
Page(s) 509 - 514
DOI https://doi.org/10.1051/ita/1995290605091
Published online 01 February 2017
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  3. 3. G. BILARDI and F. PREPARATA, Area-time lower bound techniques with application to sorting, Algorithmica, 1986, 1, pp. 65-91. [MR: 833119] [Zbl: 0622.68044]
  4. 4. G. BREBNER, Relating routing graphs and two-dimensional grids, in: Proc. VLSI: Algorithms and Architectures, North Holland, 1985. [MR: 803728] [Zbl: 0564.94019]
  5. 5. D. KLEITMAN, F. T. LEIGHTON, M. LEPLEY and G. L. MILLER, New layouts for the shuffle-exchange graph, in: Proc. 13th Annual ACM Symposium on Theory of Computing, ACM Press, 1981, pp. 278-292.
  6. 6. T. LENGAUER, Upper and lower bounds for the min-cut linear arrangements problem on trees, SIAM J. Algebraic and Discrete Methods, 1982, 3, pp. 99-113. [MR: 644961] [Zbl: 0489.68060]
  7. 7. A. D. LOPEZ and H. F. S. LAW, A dense gate matrix layout method for MOS VLSI, IEEE Trans. Electron. Devices, 1980, 27, pp. 1671-1675.
  8. 8. K. NAKANO, Linear layout of generalized hypercubes, in: Proc. 19th Intl. Workshop on Graph-Theoretic Concepts in Computer Science, Lecture Notes in Computer Science 790, Springer Verlag, Berlin, 1994, pp. 364-375. [MR: 1286286]
  9. 9. C. D. THOMPSON, Area-time complexity for VLSI, in: Proc. 11th Annual ACM Symposium on Theory of Computing, 1979, pp. 81-88. [MR: 564622]
  10. 10. J. D. ULLMAN, Computational Aspects of VLSI, Computer Science Press, Rockville, 1984. [Zbl: 0539.68021]
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