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All issues Volume 28 / No 3-4 (1994) RAIRO-Theor. Inf. Appl., 28 3-4 (1994) 159-186 References
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Issue
RAIRO-Theor. Inf. Appl.
Volume 28, Number 3-4, 1994
Special issue for Professor Karel Culik II : 60 th birthday
Page(s) 159 - 186
DOI https://doi.org/10.1051/ita/1994283-401591
Published online 03 February 2017
  1. 1. J. H. ANDERSON and M. G. GOUDA, A new explanation of the glitch phenomenon, Acta Informatica, 1991, 28, pp. 297-309. [MR: 1101643] [Zbl: 0721.94028] [Google Scholar]
  2. 2. J. A. BRZOZOWSKI and J. C. EBERGEN, Recent developments in the design of asynchronous circuits. In J. Demetrovics J. Csirik and F. Gécseg, editors, Proceedings of Fundamentals of Computation Theory, Lecture Notes in Computer Science, Berlin, Germany, August 1989. Springer-Verlag, pp. 78-94. [MR: 1033537] [Zbl: 0728.94010] [Google Scholar]
  3. 3. J. A. BRZOZOWSKI and J. C. EBERGEN, On the delay-sensitivity of gate networks, IEEE Transactions on Computers, November 1992, 41, pp. 1349-1360. [MR: 1195929] [Google Scholar]
  4. 4. J. A. BRZOZOWSKI and C.-J. H. SEGER, A characterization of ternary simulation of gate networks, IEEE Transactions on Computers, November 1987, C-36, 11, pp. 1318-1327. [Zbl: 0641.94030] [Google Scholar]
  5. 5. J. A. BRZOZOWSKI and C.-J. H. SEGER, Advances in asynchronous circuit theory part I: Gate and unbounded inertial delay models, Bulletin of the European Association of Theoretical Computer Science, 1990, 42, pp. 198-249. [Zbl: 0747.94023] [Google Scholar]
  6. 6. J. A. BRZOZOWSKI and C.-J. H. SEGER, Advances in asynchronous circuit theory part II: Bounded inertial delay models, MOS circuits, design techniques, Bulletin of the European Association of Theoretical Computer Science, 1991, 43, pp. 199-263. [Zbl: 0747.94024] [Google Scholar]
  7. 7. J. A. BRZOZOWSKI and C.-J. H. SEGER, Asynchronous Circuits, Springer-Verlag, to appear. [Google Scholar]
  8. 8. J. A. BRZOZOWSKI and M. YOELI, Digital Networks, Prentice-Hall, Inc., Englewood Cliffs, New Jersey, USA, 1976. [Google Scholar]
  9. 9. J. A. BRZOZOWSKI and M. YOELI, On a ternary model of gate networks, IEEE Transactions on Computers, 1979, C-28, 3, pp. 178-184. [MR: 523428] [Zbl: 0408.94023] [Google Scholar]
  10. 10. E. B. EICHELBERGER, Hazard detection in combinational and sequential switching circuits, IBM Journal of Research and Development, 1965, 9, pp.90-99. [Zbl: 0132.37106] [Google Scholar]
  11. 11. D. A. HUFFMAN, The synthesis of sequential switching circuits, IRE Transactions on Electronic Computers, 1954, 257, 3, pp. 161-190. [MR: 62648] [Zbl: 0166.27201] [Google Scholar]
  12. 12. D. A. HUFFMAN, The synthesis of sequential switching circuits, IRE Transactions on Electronic Computers, 1954, 257, 4, pp.275-303. [MR: 62648] [Zbl: 0166.27201] [Google Scholar]
  13. 13. Z. KOHAVI, Switching and Finite Automata Theory, Second Edition, McGraw-Hill Book Company, NewYork, NewYork, USA, 1978. [MR: 411805] [Zbl: 0384.94020] [Google Scholar]
  14. 14. M. M. MANO, Digital Design, Second Edition, Prentice-Hall, Inc., Englewood Cliffs, New Jersey, USA, 1991. [Google Scholar]
  15. 15. E. J. MCCLUSKEY, Fundamental mode and pulse mode sequential circuits. In C. M. Popplewell, editor, Proceedings of the IFIP Congress 62, Amsterdam, The Netherlands, 1963, IFIP, North-Holland Publishing Company, pp. 725-730. [Google Scholar]
  16. 16. E. J. MCCLUSKEY, Logic Design Principles, Prentice-Hall, Inc., Englewood Cliffs, New Jersey, USA, 1986. [Google Scholar]
  17. 17. C. E. MOLNAR, T. P. FANG and F. U. ROSENBERGER, Synthesis of delay-insensitive modules, In H. Fuchs, editor, Proceedings of the 1985 Chapel Hill Conference on VLSI, Rockville, Maryland, USA, 1985. Computer Science Press, pp. 67-86. [Google Scholar]
  18. 18. M. MUKAIDONO, Regular ternary logic functions - ternary logic functions suitable for treating ambiguity, In Proceedings of the 13th Annual Symposium on Multiple-Valued Logic, Los Angeles, California, USA, May 1983. IEEE, Computer Society Press, pp. 286-291. [Zbl: 0563.94019] [Google Scholar]
  19. 19. D. E. MULLER and W. S. BARTKY, A theory of asynchronous circuits, In Proceedings of an International Symposium on the Theory of Switching, Annals of the Computation Laboratory of Harvard University, Cambridge, Massachusetts, USA, 1959. Harvard University, Harvard University Press, pp. 204-243. [MR: 114698] [Zbl: 0171.37902] [Google Scholar]
  20. 20. C. E. SHANNON, A symbolic analysis of relay and switching circuits, AIEE Trans., 1938, 57, pp. 713-723. [Google Scholar]
  21. 21. S. H. UNGER, Asynchronous Sequential Switching Circuits, Wiley-Interscience, New York, New York, USA, 1969. [Google Scholar]
  22. 22. M. YOELI and I. REICHER, Synthesis of delay-insensitive circuits based on marked graphs, Technical Report 543, Department of Computer Science, Technion, Haifa, Israel, 1989. [Google Scholar]
  23. 23. M. YOELI and S. RINON, Application of ternary algebra to the study of static hazards, Journal of the ACM, 1964, 11, 1, pp. 84-97. [Zbl: 0137.33903] [Google Scholar]

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